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? semiconductor components industries, llc, 2009 october, 2009 ? rev. 1 1 publication order number: NCP5378/d NCP5378 single phase synchronous buck controller with integrated gate drivers and programmable dac the NCP5378 is a single chip solution which combines differential voltage sensing, differential phase current sensing, adaptive voltage positioning, and on board gate drivers to provide accurately regulated power for intel processors. this controller ic maintains the same features as the multi ? phase product family, but reduces the output to a single ? phase, for lower current systems. low power mode operation combined with inductor current sensing reduces system cost by providing the fastest initial response to dynamic load events. the gate drive adaptive non overlap and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. a high performance operational error amplifier is provided to simplify compensation of the system. dynamic reference injection further simplifies loop compensation by eliminating the need to compromise between closed ? loop transient response and dynamic vid performance. features ? meets intel?s vr11.1 specifications ? high performance operational error amplifier ? internal soft start ? dynamic reference injection (patent #us07057381) ? dac range from 0.5 v to 1.6 v ? 0.5% dac voltage accuracy from 1.0 v to 1.6 v ? true differential remote voltage sensing amplifier ? ?lossless? differential inductor current sensing ? adaptive voltage positioning (avp) ? latched over voltage protection (ovp) ? guaranteed startup into pre ? charged loads ? threshold sensitive enable pin for vtt sensing ? power good output with internal delays ? thermally compensated current monitoring ? thermal shutdown protection ? adaptive ? non ? overlap gate drive circuit ? integrated mosfet drivers ? automatic power ? saving modes maximize efficiency during light load operation ? 32 ? lead qfn ? this is a pb ? free device applications ? desktop power supplies for next ? generation intel chipsets http://onsemi.com marking diagram device package shipping ? ordering information qfn32 case 488am NCP5378mnr2g qfn32 (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 32 1 NCP5378 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package pin connections vcc bst tg swn vccp bg en ofs qfn ? 32 (top view) vr_rdy imon vsp vsn vfb comp diffout ilim vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 rosc vdrp dac vdfb cssum csn csp 12vmon 1 (note: microdot may be in either location)
NCP5378 http://onsemi.com 2 figure 1. functional block diagram vdrp vr_rdy vcc + ? uvlo 4.25 v gnd (flag) flexible dac vid0 vid1 vid2 vid3 vid4 vid6 vid7 + ? vsn vsp diffout + ? vfb comp 1.3 v diff amp error amp + ? overvoltage protection rpm threshold rosc ilim en + ? ilimit control, fault logic and monitor circuits vccp boot tg swn bg + ? csp csn + ? gain = 6 vid5 imon + ? uvlo + ? vdfb cssum 12vmon ofs phase 1 gate driver with adaptive non ? overlap ?
NCP5378 http://onsemi.com 3 table 1. pin descriptions pin no. symbol description 1 vr_rdy open collector output. high indicates that the output is regulating 2 imon 0 to 1 volt analog signal proportional to the output load current. vsn referenced clamped to 1.1 vmax 3 vsp non ? inverting input to the internal differential remote sense amplifier 4 vsn inverting input to the internal differential remote sense amplifier 5 vfb compensation amplifier voltage feedback 6 comp output of the compensation amplifier 7 diffout output of the differential remote sense amplifier 8 ilim over current shutdown threshold setting. ilim = vdrp ? 1.3 v. resistor divide rosc to set threshold 9 rosc a resistance from this pin to ground programs the oscillator frequency according to f sw = 1 / (rosc ? 100 pf). this pin supplies a trimmed output voltage of 2.00 v. 10 vdrp voltage output signal proportional to current used for current limit and output voltage droop 11 dac dac output used to provide feed forward for dynamic vid 12 vdfb droop amplifier voltage feedback 13 cssum inverted sum of the differential current sense inputs. 14 csn inverting input to current sense amplifier 15 csp non ? inverting input to current sense amplifier 16 12vmon monitor a 12 v input through a resistor divider 17 ofs external offset 18 en threshold sensitive input. high = startup, low = shutdown. 19 bg low side gate drive 20 vccp power vcc for gate drivers with uvlo monitor 21 swn switch node 22 tg high side gate drive 23 bst upper mosfet floating bststrap supply for driver 24 vcc power for the internal control circuits with uvlo monitor 25 vid7 voltage id dac input 26 vid6 voltage id dac input 27 vid5 voltage id dac input 28 vid4 voltage id dac input 29 vid3 voltage id dac input 30 vid2 voltage id dac input 31 vid1 voltage id dac input 32 vid0 voltage id dac input 33/ flag gnd power supply return (qfn flag)
NCP5378 http://onsemi.com 4 absolute maximum ratings rating symbol value unit electrical information controller power supply voltages to gnd v cc ? 0.3, 7 v driver power supply voltages to gnd v ccp ? 0.3, 15 v high ? side gate driver supplies: bst to swn v bst ? v swn 40 v wrt/gnd 40 v 50 ns wrt/gnd ? 0.3, 15 wrt/swn v high ? side fet gate driver voltages: tg to swn v tg ? v swn boot + 0.3 v 35 v 50 ns wrt/gnd ? 0.3, 15 wrt/swn ? 5 v (200 ns) v switch node: swn v swn 35 40 v 50 ns wrt/gnd ? 5 vdc ? 10 v (200 ns) v low ? side gate drive: bg v bg ? agnd v cc + 0.3 v ? 5 v (200 ns) v logic inputs v logic ? 0.3, 6 v gnd v gnd 0 v v ? gnd 300 mv imon out v imon 1.1 v all other pins ? 0.3, 5.5 v thermal information thermal characteristic qfn package (note 1) r ja 32.6 c/w operating junction temperature range (note 2) t j 0 to 125 c operating ambient temperature range t amb 0 to +70 c maximum storage temperature range t stg ? 55 to +150 c moisture sensitivity level qfn package msl 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *all signals referenced to gnd unless noted otherwise. *the maximum package power dissipation must be observed. 1. jesd 51 ? 5 (1s2p direct ? attach method) with 0 lfm 2. operation at ? 40 c to 0 c guaranteed by design, not production tested.
NCP5378 http://onsemi.com 5 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter test conditions min typ max unit error amplifier input bias current ? 200 ? 200 na open loop dc gain c l = 60 pf to gnd, r l = 10 k to gnd ? 100 ? db open loop unity gain bandwidth c l = 60 pf to gnd, r l = 10 k to gnd ? 18 ? mhz open loop phase margin c l = 60 pf to gnd, r l = 10 k to gnd ? 70 ? slew rate v in = 100 mv, g = ? 10v/v, v out = 1.5 v ? 2.5 v, c l = 60 pf to gnd, dc load = 125 a to gnd ? 10 ? v/ s maximum output voltage 10 mv of overdrive, i source = 2.0 ma 3.0 ? ? v minimum output voltage 10 mv of overdrive, i sink = 500 a ? ? 75 mv output source current 10 mv of overdrive, v out = 3.5 v 1.5 2.0 ? ma output sink current 10 mv of overdrive, v out = 0.1 v 0.65 1.0 ? ma differential summing amplifier v+ input pull down resistance drvon = low drvon = high ? ? 0.6 6.0 ? ? k v+ input bias voltage drvon = low drvon = high ? 0.8 0.05 0.88 0.1 0.95 v input voltage range (note 3) ? 0.3 ? 3.0 v ? 3 db bandwidth c l = 80 pf to gnd, r l = 10 k to gnd ? 15 ? mhz closed loop dc gain vs to diffout (note 3) vs+ to vs ? = 0.5 v to 1.6 v 0.98 1.0 1.02 v/v maximum output voltage 10 mv of overdrive, i source = 2 ma 3.0 ? ? v minimum output voltage 10 mv of overdrive, i sink = 1 ma ? ? 0.5 v output source current 10 mv of overdrive, v out = 3 v 1.5 2.0 ? ma output sink current 10 mv of overdrive, v out = 0.2 v 1.0 1.5 ? ma internal offset voltage offset voltage to the (+) pin of the error amp & the vdrp pin ? 2 0 +2 mv vdroop amplifier input bias current ? 200 ? 200 na inverting voltage range 0 1.3 3.0 v open loop dc gain c l = 20 pf to gnd including esd r l = 1 k to gnd ? 100 ? db open loop unity gain bandwidth c l = 20 pf to gnd including esd r l = 1 k to gnd ? 18 ? mhz 3. guaranteed by design. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
NCP5378 http://onsemi.com 6 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions vdroop amplifier open loop phase margin c l = 20 pf to gnd including esd r l = 1 k to gnd ? 70 ? slew rate c l = 20 pf to gnd including esd r l = 1 k to gnd ? 10 ? v/ s maximum output voltage 10 mv of overdrive, i source = 4.0 ma 3.0 ? ? v minimum output voltage 10 mv of overdrive, i sink = 1.0 ma ? ? 1.0 v output source current 10 mv of overdrive, v out = 3.0 v 4.0 ? ? ma output sink current 10 mv of overdrive, v out = 1.0 v 1.0 ? ? ma cssum amplifier current sense input to v drp ? 3 db bandwidth c l = 10 pf to gnd, r l = 10 k to gnd ? 12 ? mhz current summing amp output offset voltage csp ? csn = 0, csp = 1.1 v ? 16 ? +5 mv maximum cssum output voltage csp ? csn = ? 0.2 v (all phases) i source = 1 ma 3.0 ? ? v minimum cssum output voltage csp ? csn = 0.7 v (all phases) i sink = 1 ma ? ? 0.3 v output source current v out = 3.0 v 1.0 ? ? ma output sink current v out = 0.3 v 4.0 ? ? ma current sense amplifiers input bias current csp = csn = 1.4 v ? 50 ? 50 na common mode input voltage range ? 0.3 ? 2.0 v differential mode input voltage range ? 120 ? 120 mv current sharing offset csp to csn (note 3) all vios ? 2 ? 2 mv current sense input to cssum gain 0 v < csp ? csn < 0.1 v ? 3.834 ? 3.7 ? 3.574 v/v imon v drp to imon gain 1.325 v > v drp > 1.75 v 1.965 ? 2.02 v/v current sense input to v drp ? 3 db bandwidth c l = 30 pf to gnd, r l = 100 k to gnd ? 4.0 ? mhz output referred offset voltage v drp = 1.5 v, i source = 0 ma 0 23 50 mv minimum output voltage v drp = 1.3 v, i sink = 25 a ? ? 0.1 v maximum output voltage i out = 300 a 1.0 ? ? v output sink current v out = 0.3 v 175 ? ? a maximum clamp voltage imon ? vsn v drp = high r load = open 1.1 ? 1.2 v rpm threshold ramp slope (note 3) r osc = 69.8 k , dac = 1.1 v 0.175 v/ s r osc output 1.93 2.00 2.05 v vr_rdy (power good) output vr_rdy output saturation voltage i pgd = 5 ma ? ? 0.4 v vr_rdy rise time external pull ? up of 1 k to 1.25 v, c tot = 45 pf, vo = 10% to 90% ? 100 250 ns 3. guaranteed by design. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
NCP5378 http://onsemi.com 7 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions vr_rdy (power good) output vr_rdy output voltage at power ? up vr_rdy pulled up to 5 v via 2 k , t r(vcc) 3 x t r(5v) 100 s t r(vcc) 20 ms ? ? 1.0 v vr_rdy high ? output leakage current vr_rdy = 5.5 v via 1 k ? ? 0.1 a vr_rdy upper threshold voltage (intel) vcore increasing, dac = 1.3 v ? 300 250 mv (below dac) vr_rdy lower threshold voltage (intel) vcore decreasing, dac = 1.3 v 390 350 300 mv (below dac) vr_rdy rising delay vcore increasing ? 250 ? ns vr_rdy falling delay vcore decreasing ? 5.0 ? ns digital soft ? start soft ? start ramp time dac = 0 to dac = 1.1 v 1.0 ? 1.3 ms vr11 v boot time not used in legacy startup 400 500 600 s vr11 vid threshold 450 600 770 mv vr11 input bias current ? 100 ? 100 na delay before latching vid change (vid deskewing) (note 3) measured from the edge of the 1st vid change 200 ? 300 ns enable input enable high input leakage current pull ? up to 1.3 v ? ? 200 na vr11.1 threshold 450 600 770 mv enable delay time measure time from enable transitioning hi to when ss begins ? 3.5 ? ms current limit ilim to vdrp gain 0.97 1.00 1.03 v/v ilim pin input bias current ? 0.1 1.0 a ilim pin working voltage range 0.1 ? 2.0 v ilim accuracy measured with respect to the ilim setting ? 25 ? 25 mv delay ? ? 120 ns overvoltage protection vr11 over voltage threshold vid+ 180 vid+ 205 vid+ 230 mv delay ? ? 100 ns undervoltage protection v cc uvlo start threshold 4.0 4.25 4.5 v v cc uvlo stop threshold 3.8 4.05 4.3 v v cc uvlo hysteresis 150 200 ? mv 12vmon uvlo 12vmon (high threshold) v cc valid ? 0.77 0.8 v 12vmon (low threshold) v cc valid 0.4 0.68 ? v 3. guaranteed by design. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
NCP5378 http://onsemi.com 8 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions dac output output source current v out = 1.6 v 0 ? 5.0 ma output sink current v out = 0.3 v 5.0 ? 16 ma vid inputs threshold 450 600 770 mv vr11 mode leakage ? 100 ? 100 na delay before latching vid change (vid deskewing) (note 3) measured from the edge of the 1 st vid change 200 ? 300 ns digital dac slew rate limiter slew rate limit 12.5 ? 16 mv/ s soft ? start slew rate ? 0.84 ? mv/ s input supply current v cc quiescent current en low, no pwm 10 ? 30 ma v ccp supply voltage v ccp uvlo start threshold 8.2 9.0 9.5 v v ccp uvlo stop threshold 7.2 8.0 8.5 v v ccp uvlo hysteresis 1.0 ? ? v v ccp por voltage at which the driver ovp becomes active 3.0 3.2 ? boost pin uvlo boost uvlo start threshold (note 3) 3.15 4.15 v boost uvlo stop threshold (note 3) 3.0 3.85 v boost uvlo hysteresis (note 3) 50 200 ? mv startup high side short trip (active only during 1 st power on) v swx output overvoltage trip threshold at startup power startup time, v cc > 9 v 1.7 ? 2.03 v high side driver r h_tg output resistance, sourcing v bst ? v sw = 12 v ? 1.8 ? r h_tg output resistance, sinking v bst ? v sw = 12 v ? 1.0 ? tr drvh transition time c load = 3 nf, v bst ? v sw = 12 v ? 25 ? ns tf drvh transition time c load = 3 nf, v bst ? v sw = 12 v ? 20 ? ns tpdh drvh propagation delay (note 4) driving high, c load = 3.3 nf, v ccp = 12 v ? 15 ? ns low side driver r h_bg output resistance, sourcing sw = gnd ? 1.6 ? r l_bg output resistance, sinking sw = v cc ? 1.0 ? tr drvl transition time c load = 3 nf ? 20 ? ns tf drvl transition time c load = 3 nf ? 20 ? ns tpdh drvl propagation delay (note 4) driving high, c load = 3.3 nf, v ccp = 12 v ? 20 ? ns v ncdt negative current detector threshold (note 3) ? ? 4.0 ? mv 3. guaranteed by design. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
NCP5378 http://onsemi.com 9 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions thermal shutdown tsd thermal shutdown (note 3) 150 170 ? c tsdhys thermal shutdown hysteresis (note 3) ? 20 ? c vrm 11 dac system voltage accuracy 1.0 v < dac < 1.6 v 0.8 v < dac < 1.0 v 0.5 v < dac < 0.8 v ? ? ? ? ? ? 0.5 5.0 8.0 % mv mv 3. guaranteed by design. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram.
NCP5378 http://onsemi.com 10 figure 2. timing diagram tpdl drvl tf drvl tpdh drvh th drvh tpdl drvh tf drvh tr drvl tpdh drvl in drvl drvh ? sw sw 90% 2v 90% 90% 90% 10% 10% 10% 2v 10% functional descriptions general the NCP5378 is a ramp ? pulse ? modulated (rpm) controller designed with necessary features for cpu applications. the ic consists of the following blocks: precision flexible dac, dif ferential remote voltage sense amplifier, high performance voltage error amplifier, differential current feedback amplifier, precision programmable dac and pwm comparator with hysteresis. the controller also supports power saving operation at light load. protection features include: undervoltage lockout, soft start, over current protection, over voltage protection, and power good monitor. vid inputs vid0 ? vid7 control the target regulation voltage during normal operation. in vr11 mode the vid capture is enabled at the end of the v bst waiting period. if the vid is valid the dac counter will track to it. if an invalid vid occurs it will be ignored for 10 s before the controller shuts down. remote sense amplifier a high performance differential amplifier is provided to accurately sense the output voltage of the regulator. the noninverting input should be connected to the regulator?s output voltage. the inverting input should be connected to the return line of the regulator. both connection points are intended to be at a remote point so that the most accurate reading of the output voltage can be obtained. the amplifier is configured in a very unique way. first, the gain of the amplifier is internally set to unity. second, both the inverting and noninverting inputs of the amplifier are summing nodes. the inverting input sums the output voltage return voltage with the dac voltage. the noninverting input sums the remote output voltage with a 1.3 v reference. the resulting voltage at the output of the remote sense amplifier is: v diffout v out 1.3 v v dac v outreturn this signal then goes through a standard compensation circuit and into the inverting input of the error amplifier. the noninverting input of the error amplifier is also connected to the 1.3 v reference. the 1.3 v reference then is subtracted out and the error signal at the comp pin of the error amplifier is as normally expected: v comp v dac v out the noninverting input of the remote sense amplifier is pulled low through a small current si nk during a fault condition to prevent accidental charging of the regulator output. high performance voltage error amplifier a high performance voltage error amplifier is provided. the error amplifier?s inverting input and its output (the compensation pin) are both pi nned out. a standard type 3 compensation circuit is used to compensate the system. this involves a 3 pole, 2 zero compensation network. the system output current during a transient can slew as fast as 500 a/ s. the high frequency output im pedance of the system may be as low as 0.5 milli ? ohm. the pwm will need to go from a low duty cycle to full duty cycle within 100 ns. in order to respond to this magnitude of change, the output of the error amplifier must slew at a rate of at least 5 v/ s. the error amplifier output voltage needs to be able to slew from steady state to below 1.0 v or above 2.5 v. the error amplifier also needs to be very fast. the output of the error amplifier needs to respond within 50 ns to any perturbation on the input.
NCP5378 http://onsemi.com 11 the comp pin will be pulled to ground in a fault condition and should not jump up when the fault cleared. differential current feedback amplifier a differential amplifier are provided to sense the output current of each phase. the current sense amplifier senses the current through its corresponding phase. a voltage is generated across a current sense element such as an inductor or sense resistor. the sense voltage will be very low. the sense element will normally be between 0.5 m and 1.5 m . it is possible to sense both negative and positive going current. it is further possible that the differential sense signal is below 0 v. the output of these amplifiers shall not invert if the common mode range is exceeded. the gain of this amplifier is fixed and is noninverting. the output of the amplifier is used to control 3 functions. first, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. second, the output signal is fed to the current limit circuit. finally, the phase current is connected to the pwm comparator. the offset voltage difference from amplifier to amplifier and the error in bias current from amplifier to amplifier need to be minimized. the offset and bias current design needs to be able to eliminate dif ferences from amplifier to amplifier. switching frequency in rpm mode when the NCP5378 operates in rpm mode, its switching frequency is controlled by the ripple voltage on the comp pin. each time the comp pin voltage exceeds the rpm pin voltage threshold level determined by the vid voltage and the external resistor connected between rpm and ground, an internal ramp signal is started and tg is driven high. the slew rate of the internal ramp is programmed by the current entering the rosc pin. when the internal ramp signal intercepts the comp voltage, the tg pin is reset low. in continuous current mode, the switching frequency of rpm operation is almost constant. while in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current. soft start soft start is implemented internally. a digital counter steps the dac up from zero to the tar get voltage based on the predetermined rate in the spec table. the vr11 mode ramps dac to 1.1 v, pauses for 500 s, reads the dac setting, then ramps to the final dac setting. digital slew rate limiter / soft start block the slew rate limiter and the soft ? start block are to be implemented with a digital up/down counter controlled by an oscillator that can be synchronized to vid line changes. during soft start the dac will ramp at the softstart rate, after soft start is complete the ramp rate will follow the intel rate depending on the mode. in normal operation the design must keep up with the intel spec of 1 dac step every 1.25 s. the dac must be implemented down as close to zero as possible (less than 20 mv out the dac buffer) in order to avoid the output voltage jumping up at the beginning of the ramp. preferably when dac = 0 the buffer to the rs amp should deliver less than 20 mv. the digital dac offset should be introduced prior to the digital compare. protection features undervoltage lockouts an undervoltage circuit senses the input v cc and v ccp of the controller and driver voltage rail. during power up the input voltage to the controller is monitored. the pwm outputs and the soft start circuit are disabled until the input voltage exceeds the threshold voltage of the comparator. hysteresis is incorporated within the comparator. the pwm signals will control the gate status when v cc threshold is exceeded. if v cc decreases below the stop threshold, the output gate will be forced low unit input voltage v cc rises above the startup threshold. overcurrent latch a programmable overcurrent latch is incorporated within the ic. the oscillator pin provides the reference voltage for this pin. a resistor divider from this pin generates the reference voltage. the latch is set when the current information exceeds the programmed voltage. to recover the part must be reset by the en pin or by cycling v cc . the outputs will remain disabled until the v cc voltage or en is removed and reapplied. uvlo monitor if the output voltage falls greater than 300 mv below the dac voltage the uvlo comparator will trip sending the vr_rdy signal low. overvoltage protection the output voltage is monitored at the input of the differential amplifier. during normal operation, if the output voltage exceeds the dac voltage by 180 mv (or 350 mv if ofs is active), the vr_rdy flag goes low, the high side gate drivers are all brought low, and the low side gate drivers are all brought high until the voltage falls below the ovp threshold. if the over voltage trip 8 times the output voltage will shut down. the ovp will not shut down the controller if it occurs during soft ? start. this is to allow the controller to pull the output down to the dac voltage and start up into a pre ? charged output. v ccp power on reset ovp the v ccp power on reset ovp feature is used to protect the cpu during startup. when v ccp is higher than 3.2 v, the gate driver will monitor the switching node sw pin. if swn pin higher than 1.9 v, the bottom gate will be forced to high for discharge of the output capacitor . this works best if the 5 v standby is diode or?ed into v ccp with the 12 v rail. the
NCP5378 http://onsemi.com 12 fault mode will be latched unless v ccp is reduced below the uvlo threshold. power saving mode the device maintains a rpm operation in power saving mode. the 12vmon input will be used for two purposes: feedforward input supply information for rpm mode and secondary power input voltage uvlo. adaptive non ? overlap the non ? overlap dead time control is used to avoid shoot through damage to the power mosfets. when the pwm signal pull high, bg will go low after a propagation delay, the controller monitors the switching node (swn) pin voltage and the gate voltage of the mosfet to know the status of the mosfet. when the low side mosfet status is off an internal timer will delay turn on of the high?side mosfet. when the pwm pull low, gate tg will go low after the propagation delay (tpdldrvh). the time to turn off the high side mosfet is depending on the total gate charge of the high ? side mosfet. a timer will be triggered once the high side mosfet is turn off to delay the turn on the low ? side mosfet. externally programmable offset the ofs pin provides a means to program a dc current for generating an offset voltage across the resistor, r fb between fb and v diff . the offset current is generated via an external resistor and precision internal voltage references. for positive offset connect a resistor to gnd. for negative offset connect a resistor to v cc . the nominal no-load offset on NCP5378 is ? 19 mv. to set the no ? load offset please use the equations below: for negative offset connect r ofs to v cc r ofs v cc 2.0 r fb v offset for positive offset connect r ofs to gnd r ofs 0.3 r fb v offset for example to get 0 mv no-load offs et; (since the part has a nominal of -19mv) r ofs 0.3 r fb 19 mv layout guidlines layout is very important thing for design a dc ? dc converter. the strap capacitor and vin capacitor are most critical items, it should be plac ed as close as to the controller ic. another item is using a gnd plane. ground plane can provide a good return path for gate drives for reducing the ground noise. therefore gnd pin should be directly connected to the ground plane and close to the low ? side mosfet source pin. also, the gate drive trace should be considered. the gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss.
NCP5378 http://onsemi.com 13 table 2. vrm11 vid codes vid7 800 mv vid6 400 mv vid5 200 mv vid4 100 mv vid3 50 mv vid2 25 mv vid1 12.5 mv vid0 6.25 mv voltage (v) hex 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 1 0 1.60000 02 0 0 0 0 0 0 1 1 1.59375 03 0 0 0 0 0 1 0 0 1.58750 04 0 0 0 0 0 1 0 1 1.58125 05 0 0 0 0 0 1 1 0 1.57500 06 0 0 0 0 0 1 1 1 1.56875 07 0 0 0 0 1 0 0 0 1.56250 08 0 0 0 0 1 0 0 1 1.55625 09 0 0 0 0 1 0 1 0 1.55000 0a 0 0 0 0 1 0 1 1 1.54375 0b 0 0 0 0 1 1 0 0 1.53750 0c 0 0 0 0 1 1 0 1 1.53125 0d 0 0 0 0 1 1 1 0 1.52500 0e 0 0 0 0 1 1 1 1 1.51875 0f 0 0 0 1 0 0 0 0 1.51250 10 0 0 0 1 0 0 0 1 1.50625 11 0 0 0 1 0 0 1 0 1.50000 12 0 0 0 1 0 0 1 1 1.49375 13 0 0 0 1 0 1 0 0 1.48750 14 0 0 0 1 0 1 0 1 1.48125 15 0 0 0 1 0 1 1 0 1.47500 16 0 0 0 1 0 1 1 1 1.46875 17 0 0 0 1 1 0 0 0 1.46250 18 0 0 0 1 1 0 0 1 1.45625 19 0 0 0 1 1 0 1 0 1.45000 1a 0 0 0 1 1 0 1 1 1.44375 1b 0 0 0 1 1 1 0 0 1.43750 1c 0 0 0 1 1 1 0 1 1.43125 1d 0 0 0 1 1 1 1 0 1.42500 1e 0 0 0 1 1 1 1 1 1.41875 1f 0 0 1 0 0 0 0 0 1.41250 20 0 0 1 0 0 0 0 1 1.40625 21 0 0 1 0 0 0 1 0 1.40000 22 0 0 1 0 0 0 1 1 1.39375 23 0 0 1 0 0 1 0 0 1.38750 24 0 0 1 0 0 1 0 1 1.38125 25 0 0 1 0 0 1 1 0 1.37500 26 0 0 1 0 0 1 1 1 1.36875 27 0 0 1 0 1 0 0 0 1.36250 28 0 0 1 0 1 0 0 1 1.35625 29 0 0 1 0 1 0 1 0 1.35000 2a
NCP5378 http://onsemi.com 14 table 2. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 0 0 1 0 1 0 1 1 1.34375 2b 0 0 1 0 1 1 0 0 1.33750 2c 0 0 1 0 1 1 0 1 1.33125 2d 0 0 1 0 1 1 1 0 1.32500 2e 0 0 1 0 1 1 1 1 1.31875 2f 0 0 1 1 0 0 0 0 1.31250 30 0 0 1 1 0 0 0 1 1.30625 31 0 0 1 1 0 0 1 0 1.30000 32 0 0 1 1 0 0 1 1 1.29375 33 0 0 1 1 0 1 0 0 1.28750 34 0 0 1 1 0 1 0 1 1.28125 35 0 0 1 1 0 1 1 0 1.27500 36 0 0 1 1 0 1 1 1 1.26875 37 0 0 1 1 1 0 0 0 1.26250 38 0 0 1 1 1 0 0 1 1.25625 39 0 0 1 1 1 0 1 0 1.25000 3a 0 0 1 1 1 0 1 1 1.24375 3b 0 0 1 1 1 1 0 0 1.23750 3c 0 0 1 1 1 1 0 1 1.23125 3d 0 0 1 1 1 1 1 0 1.22500 3e 0 0 1 1 1 1 1 1 1.21875 3f 0 1 0 0 0 0 0 0 1.21250 40 0 1 0 0 0 0 0 1 1.20625 41 0 1 0 0 0 0 1 0 1.20000 42 0 1 0 0 0 0 1 1 1.19375 43 0 1 0 0 0 1 0 0 1.18750 44 0 1 0 0 0 1 0 1 1.18125 45 0 1 0 0 0 1 1 0 1.17500 46 0 1 0 0 0 1 1 1 1.16875 47 0 1 0 0 1 0 0 0 1.16250 48 0 1 0 0 1 0 0 1 1.15625 49 0 1 0 0 1 0 1 0 1.15000 4a 0 1 0 0 1 0 1 1 1.14375 4b 0 1 0 0 1 1 0 0 1.13750 4c 0 1 0 0 1 1 0 1 1.13125 4d 0 1 0 0 1 1 1 0 1.12500 4e 0 1 0 0 1 1 1 1 1.11875 4f 0 1 0 1 0 0 0 0 1.11250 50 0 1 0 1 0 0 0 1 1.10625 51 0 1 0 1 0 0 1 0 1.10000 52 0 1 0 1 0 0 1 1 1.09375 53 0 1 0 1 0 1 0 0 1.08750 54 0 1 0 1 0 1 0 1 1.08125 55
NCP5378 http://onsemi.com 15 table 2. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 0 1 0 1 0 1 1 0 1.07500 56 0 1 0 1 0 1 1 1 1.06875 57 0 1 0 1 1 0 0 0 1.06250 58 0 1 0 1 1 0 0 1 1.05625 59 0 1 0 1 1 0 1 0 1.05000 5a 0 1 0 1 1 0 1 1 1.04375 5b 0 1 0 1 1 1 0 0 1.03750 5c 0 1 0 1 1 1 0 1 1.03125 5d 0 1 0 1 1 1 1 0 1.02500 5e 0 1 0 1 1 1 1 1 1.01875 5f 0 1 1 0 0 0 0 0 1.01250 60 0 1 1 0 0 0 0 1 1.00625 61 0 1 1 0 0 0 1 0 1.00000 62 0 1 1 0 0 0 1 1 0.99375 63 0 1 1 0 0 1 0 0 0.98750 64 0 1 1 0 0 1 0 1 0.98125 65 0 1 1 0 0 1 1 0 0.97500 66 0 1 1 0 0 1 1 1 0.96875 67 0 1 1 0 1 0 0 0 0.96250 68 0 1 1 0 1 0 0 1 0.95625 69 0 1 1 0 1 0 1 0 0.95000 6a 0 1 1 0 1 0 1 1 0.94375 6b 0 1 1 0 1 1 0 0 0.93750 6c 0 1 1 0 1 1 0 1 0.93125 6d 0 1 1 0 1 1 1 0 0.92500 6e 0 1 1 0 1 1 1 1 0.91875 6f 0 1 1 1 0 0 0 0 0.91250 70 0 1 1 1 0 0 0 1 0.90625 71 0 1 1 1 0 0 1 0 0.90000 72 0 1 1 1 0 0 1 1 0.89375 73 0 1 1 1 0 1 0 0 0.88750 74 0 1 1 1 0 1 0 1 0.88125 75 0 1 1 1 0 1 1 0 0.87500 76 0 1 1 1 0 1 1 1 0.86875 77 0 1 1 1 1 0 0 0 0.86250 78 0 1 1 1 1 0 0 1 0.85625 79 0 1 1 1 1 0 1 0 0.85000 7a 0 1 1 1 1 0 1 1 0.84375 7b 0 1 1 1 1 1 0 0 0.83750 7c 0 1 1 1 1 1 0 1 0.83125 7d 0 1 1 1 1 1 1 0 0.82500 7e 0 1 1 1 1 1 1 1 0.81875 7f 1 0 0 0 0 0 0 0 0.81250 80
NCP5378 http://onsemi.com 16 table 2. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 1 0 0 0 0 0 0 1 0.80625 81 1 0 0 0 0 0 1 0 0.80000 82 1 0 0 0 0 0 1 1 0.79375 83 1 0 0 0 0 1 0 0 0.78750 84 1 0 0 0 0 1 0 1 0.78125 85 1 0 0 0 0 1 1 0 0.77500 86 1 0 0 0 0 1 1 1 0.76875 87 1 0 0 0 1 0 0 0 0.76250 88 1 0 0 0 1 0 0 1 0.75625 89 1 0 0 0 1 0 1 0 0.75000 8a 1 0 0 0 1 0 1 1 0.74375 8b 1 0 0 0 1 1 0 0 0.73750 8c 1 0 0 0 1 1 0 1 0.73125 8d 1 0 0 0 1 1 1 0 0.72500 8e 1 0 0 0 1 1 1 1 0.71875 8f 1 0 0 1 0 0 0 0 0.71250 90 1 0 0 1 0 0 0 1 0.70625 91 1 0 0 1 0 0 1 0 0.70000 92 1 0 0 1 0 0 1 1 0.69375 93 1 0 0 1 0 1 0 0 0.68750 94 1 0 0 1 0 1 0 1 0.68125 95 1 0 0 1 0 1 1 0 0.67500 96 1 0 0 1 0 1 1 1 0.66875 97 1 0 0 1 1 0 0 0 0.66250 98 1 0 0 1 1 0 0 1 0.65625 99 1 0 0 1 1 0 1 0 0.65000 9a 1 0 0 1 1 0 1 1 0.64375 9b 1 0 0 1 1 1 0 0 0.63750 9c 1 0 0 1 1 1 0 1 0.63125 9d 1 0 0 1 1 1 1 0 0.62500 9e 1 0 0 1 1 1 1 1 0.61875 9f 1 0 1 0 0 0 0 0 0.61250 a0 1 0 1 0 0 0 0 1 0.60625 a1 1 0 1 0 0 0 1 0 0.60000 a2 1 0 1 0 0 0 1 1 0.59375 a3 1 0 1 0 0 1 0 0 0.58750 a4 1 0 1 0 0 1 0 1 0.58125 a5 1 0 1 0 0 1 1 0 0.57500 a6 1 0 1 0 0 1 1 1 0.56875 a7 1 0 1 0 1 0 0 0 0.56250 a8 1 0 1 0 1 0 0 1 0.55625 a9 1 0 1 0 1 0 1 0 0.55000 aa 1 0 1 0 1 0 1 1 0.54375 ab
NCP5378 http://onsemi.com 17 table 2. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 1 0 1 0 1 1 0 0 0.53750 ac 1 0 1 0 1 1 0 1 0.53125 ad 1 0 1 0 1 1 1 0 0.52500 ae 1 0 1 0 1 1 1 1 0.51875 af 1 0 1 1 0 0 0 0 0.51250 b0 1 0 1 1 0 0 0 1 0.50625 b1 1 0 1 1 0 0 1 0 0.50000 b2 1 1 1 1 1 1 1 0 off fe 1 1 1 1 1 1 1 1 off ff 5. note: internal dac voltage is centered 19 mv below the listed voltage for vr11.1.
NCP5378 http://onsemi.com 18 package dimensions qfn32 5x5, 0.5p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5378/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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